Title :
Through-Silicon-Via stress 3D modeling and design
Author :
Dao, Thuy ; Adams, Vance
Author_Institution :
Freescale Semicond., Austin, TX, USA
Abstract :
Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al, and the proposed stress measurement and model has been reported by Chidambaram et. al. Finite element method (FEM) 3D simulation has been used to model the localized stress fields at the surrounding substrate area for W-filled TSVs, and this simulation has been verifiably correlated to the CRM and EBSD measurement results. In this paper, to help in determining circuit layout design rules, FEM is extensively used in evaluating the impact of TSV size, length and spacing on the induced stress to the nearby silicon substrate.
Keywords :
circuit simulation; finite element analysis; integrated circuit design; integrated circuit modelling; thermal expansion; three-dimensional integrated circuits; 3D chip stacked integrated circuit; CRM measurement; CTE mismatch; EBSD measurement; FEM 3D simulation; TSV processing; circuit design; circuit layout design; circuit production; coefficient of thermal expansion; copper-filled TSV; finite element method; induced stress; stress measurement; through-silicon-via stress 3D modeling; Circuit simulation; Circuit synthesis; Copper; Integrated circuit technology; Silicon; Stress measurement; Thermal expansion; Thermal management; Thermal stresses; Through-silicon vias;
Conference_Titel :
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4244-5773-1
DOI :
10.1109/ICICDT.2010.5510281
