A new design approach to VLSI parallel implementation of discrete Hartley transform

In this paper, an efficient approach to design VLSI arrays for prime length discrete Hartley transform (DHT) with high throughput and low hardware complexity is proposed. The presented approach is based on an adequate decomposition of the DHT transform in two related subproblems which are efficiently converted into similar cyclic convolution forms and mapped into a single linear systolic array. Thus, the hardware complexity is reduced as much as possible. The properties of the Galois field are used to rearrange I/O data such that the two subproblems are efficiently reformulated as cyclic convolution forms with similar structure. Thus, the two subproblems can be computed in parallel on a single systolic array, obtaining high computing speeds with a low hardware complexity of PEs. Moreover, due to the fact that the same biport ROM can be used to implement the both multipliers from each PE a further reduction of the hardware complexity can be obtained. Hence, the proposed systolic array has outstanding performance in hardware cost of the processing elements, average computation time, and I/O cost