DocumentCode
3031174
Title
Impact of resistance drift on multilevel PCM design
Author
Chiu, Yi-Hsuan ; Liao, Yi-Bo ; Chiang, Meng-Hsueh ; Lin, Chia-Long ; Hsu, Wei-Chou ; Chiang, Pei-Chia ; Hsu, Yen-Ya ; Liu, Wen-Hsing ; Sheu, Shyh-Shyuan ; Su, Keng-Li ; Kao, Ming-Jer ; Tsai, Ming-Jinn
Author_Institution
Dept. of Electron. Eng., Nat. Ilan Univ., Ilan, Taiwan
fYear
2010
fDate
2-4 June 2010
Firstpage
20
Lastpage
23
Abstract
Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.
Keywords
phase change memories; multilevel PCM design; multilevel phase change memory; resistance drift; Amorphous materials; Computer industry; Crystallization; Electrical resistance measurement; Electronics industry; Industrial electronics; Nonvolatile memory; Phase change materials; Space vector pulse width modulation; Temperature; Phase change memory (PCM); compact model; multilevel cell (MLC); resistance drift;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location
Grenoble
Print_ISBN
978-1-4244-5773-1
Type
conf
DOI
10.1109/ICICDT.2010.5510298
Filename
5510298
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