On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

We examine the complex relationship between experimentally-measured power penalty performance metrics of a silicon photonic modulator, and its broad impact on the throughput performance of a full-scale on-chip optical interconnection network. Using our physically-accurate network-level simulation environment, we further evaluate this impact from hypothetical device performance improvements. The results indicate that in order to achieve the highest throughput, an intricate balance must be reached between modulation rate and device performance.