Capturing intrinsic impact of low-k dielectric stacks and packaging materials on mechanical integrity of Cu/low-k interconnects

Author

Furusawa, Takeshi ; Goto, Kinya ; Izumitani, Junko ; Matsuura, Masazumi ; Fujisawa, Masahiko ; Kawanabe, Naoki ; Hirose, Tetsuya ; Hayashi, Eiji ; Baba, Shinji ; Asano, Yoshinobu ; Ichiki, Tsutomu ; Takata, Yoshifumi

Author_Institution

Renesas Technol. Corp., Ibaraki, Japan

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

We present a methodology for capturing the intrinsic impact of both low-k dielectric stacks and packaging materials on the mechanical integrity of Cu/low-k interconnects. This drastically reduces the time and cost of sample fabrication and reliability tests and provides short-cycle feedback for both low-k and packaging materials development. Furthermore, this methodology is applicable for all types of packaging, from low-cost QFPs to high-performance Pb-free FCBGAs.

Keywords

copper; electronics packaging; integrated circuit interconnections; integrated circuit reliability; low-k dielectric thin films; Cu/low-k interconnect; Pb-free FCBGA; low-cost QFP; low-k dielectric stack; mechanical integrity; packaging material; Costs; Delamination; Dielectric materials; Electronics packaging; Feedback; Inorganic materials; Materials reliability; Materials testing; Resins; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510312

Filename

5510312