• DocumentCode
    3031535
  • Title

    Effective iterative techniques for fingerprinting design IP [VLSI CAD]

  • Author

    Caldwell, Andrew E. ; Choi, Hyun-Jin ; Kahng, Andrew B. ; Mantik, Stefanus ; Potkonjak, Miodrag ; Qu, Gang ; Wong, Jennifer L.

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    843
  • Lastpage
    848
  • Abstract
    While previous watermarking-based approaches to intellectual property protection (IPP) have asymmetrically emphasized the IP provider´s rights, the true goal of IPP is to ensure the rights of both the IP provider and the IP buyer. Symmetric fingerprinting schemes have been widely and effectively used to achieve this goal; however, their application domain has been restricted only to static artifacts, such as image and audio. In this paper, we propose the first generic symmetric fingerprinting technique which can be applied to an arbitrary optimization/synthesis problem and, therefore, to hardware and software intellectual property. The key idea is to apply iterative optimization in an incremental fashion to solve a fingerprinted instance; this leverages the optimization effort already spent in obtaining a previous solution, yet generates a uniquely fingerprinted new solution. We use this approach as the basis for developing specific fingerprinting techniques for four important problems in VLSI CAD: partitioning, graph coloring, satisfiability, and standard-cell placement. We demonstrate the effectiveness of our fingerprinting techniques on a number of standard benchmarks for these tasks. Our approach provides an effective tradeoff between runtime and resilience against collusion
  • Keywords
    VLSI; circuit CAD; circuit layout CAD; computability; graph colouring; industrial property; integrated circuit design; integrated circuit layout; iterative methods; VLSI CAD; generic symmetric fingerprinting technique; graph coloring; hardware intellectual property; intellectual property protection; iterative optimization; iterative techniques; partitioning; satisfiability; software intellectual property; standard-cell placement; Design automation; Fingerprint recognition; Intellectual property; Iterative methods; Law; Legal factors; Process design; Protection; Very large scale integration; Watermarking;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1999. Proceedings. 36th
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    1-58113-092-9
  • Type

    conf

  • DOI
    10.1109/DAC.1999.782157
  • Filename
    782157