DocumentCode
3031629
Title
Converting a 64 b PowerPC processor from CMOS bulk to SOI technology
Author
Allen, D. ; Behrends, D. ; Stanisic, B.
Author_Institution
IBM Corp., Rochester, MN, USA
fYear
1999
fDate
1999
Firstpage
892
Lastpage
897
Abstract
A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI
Keywords
CMOS digital integrated circuits; circuit CAD; integrated circuit design; microprocessor chips; silicon-on-insulator; timing; 550 MHz; 64 bit; CAD methodology; CMOS SOI technology; IC design; PowerPC processor; Si; chip integration methodologies; circuit design; cycle time; timing; CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Circuit synthesis; Copper; Design automation; Logic arrays; Silicon on insulator technology; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location
New Orleans, LA
Print_ISBN
1-58113-092-9
Type
conf
DOI
10.1109/DAC.1999.782211
Filename
782211
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