Low-cost real-time stereo vision hardware with binary confidence metric and disparity refinement

This paper presents a real-time stereo vision System-on-Chip (SoC) architecture for a depth-field generation processor as required in 3D TV applications. This architecture includes post-processing steps like a decision tree based confidence metric and a disparity refinement module while still fitting in a low cost FPGA. A real-time stereo matching calculation at a frame rate of 56 Hz with a resolution of 800 × 600 and a disparity of 80 has been realized using this architecture without the need for external memories.