Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels

Summary form only given. The real-time application of trellis coding to partial response channels is described for a rate 8/10 matched-spectral-null (MSN) trellis code on the (1-D) partial response channel. The architectural and design issues of an experimental chip that implements the functions of encoding, decoding, and Viterbi detection are discussed. Two novel techniques in the design of the Viterbi detector are introduced. Modulo normalization of the path metrics, and area-efficient pipelining for the add-compare-select units. Both techniques are effective in producing a regular structure and reducing the number of required interconnections. Area-efficient realization is achieved with little speed degradation. The circuit and layout were designed using LAGER CAD tool. The chip was fabricated in 1.2 μm CMOS