VLSI asynchronous sequential circuit design

A novel design procedure for VLSI asynchronous sequential circuits is presented. It is based on partition algebra and generates circuits that use fewer transistors compared to previous procedures. This design procedure is simple and produces circuits that have very regular structures and are faster compared to the circuits generated by the existing procedures. This is due to the reduced number of transistors in the chain connected to the buffer. The circuits are generated by replication of similar units. This leads to a regular layout, and the small blocks can be optimized for optimum performance. This procedure can be extended to synchronous sequential machine design by replacing the buffer with a D flip-flop