An approach to 150 K gate low power ECL cell based integrated circuits

Author

Taylor, G. ; Sanguinetti, G. ; Lane, R.

fYear

1990

fDate

17-19 Sep 1990

Firstpage

263

Lastpage

268

Abstract

A technology and a design system for implementing VLSI ECL circuits with 50 to 150 K gates is described. The technology provides high-density ECL logic and BiCMOS RAMs, while the design system avoids many of the hand checks previously required for successful ECL designs. System design considerations, standard cell based design methodology, design verification, and process technology are outlined

Keywords

VLSI; emitter-coupled logic; integrated logic circuits; logic design; 150 K gate low power ECL cell based integrated circuits; BiCMOS RAMs; VLSI; design verification; process technology; standard cell based design methodology; system design; Bipolar integrated circuits; Capacitance; Clocks; Delay; Integrated circuit technology; Logic design; Power supplies; Process design; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130222

Filename

130222

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3032176