Design and application trade-offs between high-density and high-speed ASICs

Author

Lampin, P. ; Le Garrec, J.C. ; Marion, C. ; Mifsud, J.P. ; Mille, T. ; Nicot, S. ; Rousseau, B. ; Saura, R. ; Tatry, T. ; Glossner, C.J. ; Kilmoyer, R.D.

Author_Institution

IBM Gen. Technol. Div., Corbeil-Essonnes, France

fYear

1990

fDate

17-19 Sep 1990

Firstpage

269

Lastpage

272

Abstract

Two CMOS application-specific integrated circuit (ASIC) families are presented. The first ASIC family with 1.0 μm channel length, is based on a sea-of-cells (SOC) architecture and a double-level-metal (DLM) structure. It offers chip density up to 100 K wirable circuits and higher I/O pin count using plastic-flat-pack (PFP) packaging. The second ASIC family with 0.5 μm channel length offers up to 75 K wirable gates with boundary scan I/Os and array built-in self-test (ABIST). Single-chip-module (SCM), and multiple-chip-module (MCM) pin-in-hole packages are used to save space at the card level. Specific features are described, focusing on the complementarity offering of these two families and on the design tradeoffs between high-density and high-speed ASIC applications

Keywords

CMOS integrated circuits; application specific integrated circuits; built-in self test; integrated circuit testing; packaging; 0.5 micron; 1 micron; CMOS; application trade-offs; array built-in self-test; design tradeoffs; double-level-metal; high-density ASICs; high-speed ASICs; multiple-chip-module; packaging; pin-in-hole packages; plastic-flat-pack; sea-of-cells; single-chip module; Application software; Application specific integrated circuits; CMOS technology; History; Integrated circuit technology; Packaging; Routing; Space technology; Voltage; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130223

Filename

130223