On the testability of realistic bridging faults

Author

Santos, M.B. ; Sousa, J.J.T. ; Goncalves, Felipe M. ; Teixeira, J.P.

Author_Institution

INESC, IST, Lisboa, Portugal

fYear

1991

fDate

18-20 Nov 1991

Firstpage

175

Lastpage

178

Abstract

Discusses the preliminary simulation results concerning the coverage of realistic bridging faults, according to an experimental fault classification of node shorts between logic nodes. There is evidence to support that, prior to simulation, difficult to detect faults can be identified, according to their topological characteristics. This may allow the definition of manageable subsets of bridging faults, whose avoidance by layout reconfiguration may be rewarding

Keywords

CMOS integrated circuits; VLSI; integrated circuit testing; logic testing; CMOS; VLSI; bridging faults; difficult to detect faults; experimental fault classification; fault coverage; layout reconfiguration; logic nodes; node shorts; preliminary simulation results; realistic faults; subsets of bridging faults; testability; topological characteristics; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Logic devices; Packaging; Reconfigurable logic; Semiconductor device measurement; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on

Conference_Location

Hidden Valley, PA

ISSN

1550-5774

Print_ISBN

0-8186-2457-4

Type

conf

DOI

10.1109/DFTVS.1991.199959

Filename

199959