Concurrent built-in self-test with reduced fault latency

Presents various new approaches for concurrent built-in self-test (CBIST). These new approaches have a low latency in fault detection. Two approaches are proposed. The first approach is applicable to combinational logic circuits which can be designed using iterative logic arrays (ILAs). Two methods namely the HIT-COMPRESS and HIT-IDENTICAL, are discussed. These methods employ different hardware structures to accomplish on-line detection. The second approach is applicable to sequential circuits. Two implementations are presented. The first implementation is based on a ring counter, while the second implementation utilizes a parity tree. The principles of operation of these approaches have been fully analyzed and it is proved that fault latency is considerably less than in previous approaches. Hardware overhead issues are also analyzed