Title :
Array architecture for ATG with 100% fault coverage
Author :
El-Ayat, Khaled ; Cahn, R. ; Chan, Chung Lau ; Speers, Ted
Author_Institution :
Actel Corp., Sunnyvale, CA, USA
Abstract :
Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results
Keywords :
integrated circuit testing; logic arrays; logic testing; 100% fault coverage; ATG; FPGA; Hard Array; array architecture; automatic generation of test vectors; automatic test generation; circuit implementation; circuit overhead; controllability; generation methodology; mask programmable gate arrays; observability; test features; test times; Application specific integrated circuits; Automatic testing; Circuit faults; Circuit testing; Costs; Field programmable gate arrays; Logic arrays; Logic testing; Programmable logic arrays; Routing;
Conference_Titel :
Defect and Fault Tolerance on VLSI Systems, 1991. Proceedings., 1991 International Workshop on
Conference_Location :
Hidden Valley, PA
Print_ISBN :
0-8186-2457-4
DOI :
10.1109/DFTVS.1991.199966
