Electronic implementation for competitive neural network: a prototype

Presents the circuit implementation for an electronic neural network which is composed of pulsed-neurons and pulse width weighting synaptic links, based on programmable logic devices and standard electronic parts. The resulting prototype circuit is useful for emulating in real time two-layer feedforward and competitive neural architectures as demonstrated by a two-input, three-output classification system. The technique that supports this circuit is based on both the pulse coded and the pulse-stream arithmetic methodologies