Title :
PANTHER: a parallel neuro-systolic architecture for real-time processing
Author :
Patel, Minesh I. ; Ranganathan, N.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
In this paper, we describe a parallel neuro-systolic architecture called PANTHER for use in real-time applications. The architecture is a special purpose, backpropagation based linear neural network. The PEs in the array are capable of computing several neural functions. A two-stage sigmoid generator block is used instead of lookup tables as a means for activation function generation. Additionally, reduced precision arithmetic is employed to avoid floating point computation and hardware. The neural network is composed of a linear systolic array of simple PEs that are easily configurable to meet any neural topology. The neural network architecture can be integrated with an expert system in order to realize an intelligent decision making system. Such a system is currently being investigated and some results for the robotic obstacle avoidance problem are reported in this paper. The proposed hardware is expected to yield a response time of 5 ns per decision based on a 200 MHz clock
Keywords :
VLSI; backpropagation; network topology; neural chips; neural net architecture; neurocontrollers; path planning; real-time systems; robots; systolic arrays; PANTHER; backpropagation; intelligent decision making system; linear neural network; neural topology; neuro-systolic architecture; parallel architecture; real-time processing; reduced precision arithmetic; robotic obstacle avoidance; sigmoid generator; Backpropagation; Computer architecture; Expert systems; Floating-point arithmetic; Hardware; Intelligent systems; Network topology; Neural networks; Systolic arrays; Table lookup;
Conference_Titel :
Neural Networks, 1996., IEEE International Conference on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3210-5
DOI :
10.1109/ICNN.1996.549035