• DocumentCode
    3033438
  • Title

    Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs

  • Author

    Yoshitomi, T. ; Saito, M. ; Ohguro, T. ; Ono, M. ; Momose, H.S. ; Iwai, H.

  • Author_Institution
    Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
  • fYear
    1995
  • fDate
    6-8 June 1995
  • Firstpage
    11
  • Lastpage
    12
  • Abstract
    Silicided Silicon-Sidewall Source and Drain (S/sup 4/D) structures were proposed for sub-0.1 /spl mu/m gate length p-MOSFETs as the structure which can realize extremely small source and drain series resistance with small short-channel effects. By using this structure, 75 mm gate length p-MOSFETs were fabricated and very good electrical characteristics were confirmed. In this experiment, only p-MOSFETs were fabricated, but the S/sup 4/D structures are also suitable for the sub-0.1 /spl mu/m gate length CMOS devices, because, basically, the sidewall amorphous silicon is easily doped with the dopant of source and drain by source and drain implantation without prior in situ doping.
  • Keywords
    MOSFET; amorphous semiconductors; elemental semiconductors; ion implantation; semiconductor device metallisation; silicon; 75 nm; S/sup 4/D structures; Si; drain implantation; electrical characteristics; gate length; pMOSFETs; series resistance; short-channel effects; sidewall amorphous silicon; silicided silicon-sidewall source and drain; source implantation; Boron; Contact resistance; Electrodes; Fabrication; Impurities; Ion implantation; MOSFET circuits; Silicides; Silicon; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    0-7803-2602-4
  • Type

    conf

  • DOI
    10.1109/VLSIT.1995.520835
  • Filename
    520835