Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices

In order to maintain the historical scaling of computational power in information processing beyond the 2020 technology node, switches that are based on state variables other than electron charge are currently being investigated. Examples of alternate state variables include the electron spin, pseudo-spin in graphene, and excitons. This paper discusses different communication mechanisms for on-chip local interconnects for post-CMOS devices. Models for delay and energy dissipation for novel interconnects are obtained, and a comparison is provided with their CMOS counterpart. It is shown that novel interconnects can potentially consume less energy per bit as compared to the CMOS interconnects. However, they pose significant delay penalty. The paper highlights some of the major implications of the novel interconnects on the post-CMOS circuits.