DocumentCode
3033575
Title
Pin assignment for improved performance in standard cell design
Author
Marek-Sadowska, Malgorzata ; Lin, Shen P.
Author_Institution
Electron. Res. Lab., California Univ., Berkeley, CA, USA
fYear
1990
fDate
17-19 Sep 1990
Firstpage
339
Lastpage
342
Abstract
Chip performance optimization is a crucial task in the modern design process. A method to improve the longest delay in a circuit built for standard cells is discussed. The method used to improve the designs is attractive because it does not require an increase in active area. All the improvements are achieved by a careful pin assignment. An efficient pin assignment algorithm is proposed. It has been implemented and the results are very encouraging
Keywords
circuit layout CAD; delays; active area; chip performance optimization; delay analysis; longest delay; pin assignment algorithm; standard cell design; standard cells; Capacitance; Circuits; Delay; Electric resistance; Laboratories; Libraries; Logic; Pins; Switches; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2079-X
Type
conf
DOI
10.1109/ICCD.1990.130244
Filename
130244
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