DocumentCode :
3033604
Title :
Optimal FPGA implementation of GARBF systems
Author :
Vizitiu, I.C. ; Rîncu, I.C. ; Radu, A. ; Nicolaescu, I. ; Popescu, F.
Author_Institution :
Commun. & Electron. Syst. Dept., MTA, Bucharest, Romania
fYear :
2010
fDate :
20-22 May 2010
Firstpage :
774
Lastpage :
779
Abstract :
One of the most important methods to increase the performance level of real-time neural pattern recognition systems is to use efficient hardware architectures inside of their classification chains. Consequently, a genetic procedure used for optimal center selection and training of RBF neural networks (GARBF system) is described. Finally, to confirm the experimental results achieving by software simulations, a proper FPGA implementation of RBF neural networks is also proposed.
Keywords :
circuit optimisation; field programmable gate arrays; logic design; pattern recognition equipment; radial basis function networks; FPGA; GARBF system; RBF neural network; hardware architecture; neural pattern recognition system; Computer architecture; Electronic equipment; Encoding; Field programmable gate arrays; Genetic algorithms; Neural network hardware; Neural networks; Optimization methods; Pattern recognition; Real time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Optimization of Electrical and Electronic Equipment (OPTIM), 2010 12th International Conference on
Conference_Location :
Basov
ISSN :
1842-0133
Print_ISBN :
978-1-4244-7019-8
Type :
conf
DOI :
10.1109/OPTIM.2010.5510449
Filename :
5510449
Link To Document :
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