Radiation-hardened phase-locked loop fabricated in 200 nm SOI-CMOS

Author

Matsuura, D. ; Hirose, K. ; Kobayashi, D. ; Ishii, S. ; Kusano, M. ; Kuroda, Y. ; Saito, H.

Author_Institution

Mitsubishi Heavy Ind. Ltd., Komaki, Japan

fYear

2011

fDate

19-23 Sept. 2011

Firstpage

150

Lastpage

155

Abstract

We designed a phase-locked loop (PLL) operating at 200 MHz using 0.2 μm fully depleted silicon-on-insulator (SOI) technology. By SPICE simulation with an appropriate single-event transient (SET) model, we achieved a radiation-hardened PLL that does not cause a SET upset upon ion irradiation with a linear energy transfer (LET) of 50 MeV-cm²/mg at an areal penalty of 75%.

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit design; phase locked loops; radiation hardening (electronics); silicon; silicon-on-insulator; CMOS technology; LET; SET model; SOI technology; SPICE simulation; Si; frequency 200 MHz; ion irradiation; linear energy transfer; radiation-hardened PLL fabrication; radiation-hardened phase-locked loop fabrication; silicon-on-insulator technology; single-event transient model; size 0.2 mum; Impedance; Integrated circuit modeling; MOSFETs; Phase locked loops; SPICE; Solid modeling; phase-locked loop (PLL); radiation effects; radiation-hardened-by-design (RHBD); single-event transient (SET);

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on

Conference_Location

Sevilla

ISSN

0379-6566

Print_ISBN

978-1-4577-0585-4

Type

conf

DOI

10.1109/RADECS.2011.6131388

Filename

6131388