A sorting-based architecture of finding the first two minimum values for LDPC decoding

This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min_1st, second minimum value, min_2nd and the position of min_1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.