DocumentCode :
3033984
Title :
Two-stage lot scheduling with waiting time constraints and due dates
Author :
Tae-Sun Yu ; Hyun-Jung Kim ; Chanhwi Jung ; Tae-Eog Lee
Author_Institution :
Dept. of Ind. & Syst. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
fYear :
2013
fDate :
8-11 Dec. 2013
Firstpage :
3630
Lastpage :
3641
Abstract :
We examine a two-stage lot scheduling problem with waiting time constraints and distinct due dates. Wafer lots in diffusion or etch processes generally have due dates specified for each process stage. Some lots even have more strict time constraints that their waiting times between two or multiple stages should not exceed specified limits. We also wish to minimize the variation of the waiting times at the intermediate buffer, which is detrimental to wafer quality variability. To solve such a scheduling problem, we develop a mixed integer programming model for small problems. Also, we suggest an efficient solution procedure for large problems by adopting the earliest due date policy and propose a timing control strategy.
Keywords :
integer programming; quality control; scheduling; semiconductor industry; semiconductor technology; earliest due date policy; intermediate buffer; mixed integer programming model; process stage; timing control strategy; two-stage lot scheduling problem; wafer quality variability; waiting time constraints; Industries; Job shop scheduling; Linear programming; Optimal scheduling; Process control; Time factors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation Conference (WSC), 2013 Winter
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4799-2077-8
Type :
conf
DOI :
10.1109/WSC.2013.6721724
Filename :
6721724
Link To Document :
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