SET susceptibility analysis in buffered tree clock distribution networks

Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. Preliminary results investigate SET propagation in two clock networks. By using the proposed methodology, it is possible to evaluate alternative clock network designs constraints such as different number and size of buffers, clock gating and fan-out branch paths. Each solution may lead into a distinct SET susceptibility clock network map.