Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering

Author

Fujii, K. ; Kikuta, K. ; Kikkawa, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1995

fDate

6-8 June 1995

Firstpage

57

Lastpage

58

Abstract

A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.

Keywords

CMOS integrated circuits; integrated circuit metallisation; sputter deposition; titanium compounds; 0.20 micron; C49-to-C54 phase transition; CMOS transistors; TiSi/sub 2/; diffusion layers; effective channel length; gates; high-temperature sputtering; in-situ silicidation; sheet resistance; sub-quarter micron titanium salicide technology; Atmosphere; CMOS process; Implants; Leakage current; Silicidation; Silicides; Sputtering; Temperature; Titanium; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7803-2602-4

Type

conf

DOI

10.1109/VLSIT.1995.520856

Filename

520856