Title :
A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process
Author :
Nakamura, H. ; Horiuchi, T.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.
Keywords :
CMOS integrated circuits; channelling; integrated circuit technology; ion implantation; 0.25 micron; 0.9 V; CMOS process; channeling ion implantation; inverter chain; junction capacitance; propagation delay time; self-aligned counter well-doping; Boron; CMOS process; CMOS technology; Costs; Counting circuits; Doping; Impurities; Ion implantation; Parasitic capacitance; Ultra large scale integration;
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
DOI :
10.1109/VLSIT.1995.520861
