Chip scale package (CSP) "a lightly dressed LSI chip"

Smallest packages accompanied by excellent testabilities are requested by the industry for both single chip packaging and MCM (Multi Chip Module) application. To meet with the requirements, we designed a new flip-chiplike package. This package has two features. One is the "package" feature, easy to handle, to test and to standardize. The other is the "bare chip" feature, smallest in size, providing highest mount density and enhanced electrical performance. This package is named CSP after these two features. Several process improvements involving material selections have been executed in the package development. In wiring (metallization) process, combinations of metals were studied so that it could serve as sufficient diffusion barrier, while providing oxidation resistivity, good wettability and sufficient dissolution life. The experimental results are explained in this paper. Also, a transfer-bumping technique applied in this package fabrication is discussed focusing on how we controlled the transferabilities. Finally, simulations on the solder joints fatigue life are introduced.