Logical circuit gate sizing using MPSO guided by Logical Effort - An examination of the 8-stage full adder circuit

Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use repetitive manual testing guided by Logical Effort (LE). Our previous works have shown the applicability of the Particle Swarm Optimization (PSO) algorithm guided by LE in searching for optimal gate widths for CMOS design. In this paper, we present a PSO variant called Mutative Particle Swarm Optimization (MPSO) to automate the sizing process of CMOS circuit design on an 8-stage full adder circuit. In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, with the solution fitness guided by the LE method. Various parameters, such as swarm size and iterations were tested under different initialization conditions to verify MPSO´s performance on a 8-stage full-adder circuit. Results have indicated that the MPSO algorithm was an effective method to apply to the circuit design problem, with high convergence rates observed.