Title :
Methods for memory test time reduction
Author :
Wu, Wen-Jer ; Tang, Chuan Yi ; Lin, Mike Y.
Author_Institution :
National Tsing-Hua University
Keywords :
Algorithm design and analysis; Assembly; Computer science; Failure analysis; Heuristic algorithms; Industrial relations; Polynomials; Testing; Timing; Voltage;
Conference_Titel :
Memory Technology, Design and Testing, 1996. Records of the 1996 IEEE International Workshop on
Print_ISBN :
0-8186-7466-0
DOI :
10.1109/MTDT.1996.782494
