Title :
Design-for-test analysis of a buffered sdram dimm
Author :
Jandhyala, Sri ; Ley, Adam
Author_Institution :
Texas Instruments
Keywords :
Assembly; Circuit testing; Clocks; Costs; Design for testability; Manufacturing; Modular construction; SDRAM; Surface-mount technology; System testing;
Conference_Titel :
Memory Technology, Design and Testing, 1996. Records of the 1996 IEEE International Workshop on
Print_ISBN :
0-8186-7466-0
DOI :
10.1109/MTDT.1996.782501
