DocumentCode

3035410

Title

Design-for-test analysis of a buffered sdram dimm

Author

Jandhyala, Sri ; Ley, Adam

Author_Institution

Texas Instruments

fYear

1996

fDate

1996

Firstpage

110

Lastpage

116

Keywords

Assembly; Circuit testing; Clocks; Costs; Design for testability; Manufacturing; Modular construction; SDRAM; Surface-mount technology; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1996. Records of the 1996 IEEE International Workshop on

ISSN

1087-4852

Print_ISBN

0-8186-7466-0

Type

conf

DOI

10.1109/MTDT.1996.782501

Filename

782501