Hardware implementation of convolution using number theoretic transforms

Using the Residue Number System (RNS) as a basis for the hardware construction, two different hard-ware structures are discussed for implementing NTTs over a direct sum of Galois Fields GF(mi²). The first structure uses arrays of read only memories and the second uses arrays of microprocessors; in particular, single chip microprocessors are proposed. The two techniques offer trade offs between speed of operation, and cost. Using the RNS, rather than conventional binary arithmetic, allows more flexibility in the choice of the generator, α, and consequently more flexibility in allowable transform parameters. A selection of parameters, for the two realizations, are discussed when the Galois Field of mi²elements is a finite field of Gaussian or quadratic integers.