Title :
Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications
Author :
Keshavarzi, A. ; Somasekhar, D. ; Rashed, M. ; Ahmed, S. ; Maitra, K. ; Miller, R. ; Knorr, A. ; Cho, Jin ; Augur, R. ; Banna, S. ; Shaw, C.-H. ; Halliyal, A. ; Schroeder, U. ; Wei, A. ; Egley, J. ; Korablev, K. ; Luning, S. ; Lin, M.-R. ; Venkatesan, S.
Author_Institution :
Adv. Technol. Archit., R&D Group, GlobalFoundries, Sunnyvale, CA, USA
Abstract :
The idea is to integrate the transistor and physical scaling benefits to offer a cost sensitive technology platform that provides value for the SoC applications and effectively for the end users.the complexity of achieving this task to minimize the risk and TTV/TTM while addressing the difficult technical barriers. Device and circuit co-optimization enhances the SoC values measured by PPC, PPA, and Fmax.
Keywords :
MOSFET; circuit optimisation; system-on-chip; 3D FinFET transistor; Fmax; PPA; PPC; SoC application; TTV-TTM; advanced technology architecture; circuit cooptimization; cost sensitive technology; physical scaling benefit; size 14 nm; Doping; FinFETs; Logic gates; Performance evaluation; Random access memory; Strain; System-on-a-chip;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131485
