Novel VTH self-adjusting MISFET with SiN charge trap layer for ultra low power LSI

A novel V_TH self-adjusting FET with SiN charge trap layer is proposed and experimentally demonstrated. The V_TH self-adjusting FET has a poly Si/SiN/SiO₂/Si gate stack and can be introduced to conventional CMOS platform with a small additional cost. The |V_TH| of the V_TH self-adjusting nFET and pFET decrease on on-state and come back to the initial high value on off-state due to charging and neutralization of the SiN layer by exchange of electrons with gate electrode. The dynamic V_TH tuning ability improves both of read and write margins of SRAM. V_TH tuning ability of 100mV is achieved by Si-rich SiN film of less than 1nm, which leads to reduction of minimum operating voltage (V_{DD_min}) of SRAM by 170mV. It is found that switching energy efficiency (energy per a cycle) can be improved largely beyond the limit of conventional FET in ultra low V_DD region by V_TH self-adjusting function.