Statistical variability and reliability in nanoscale FinFETs

Author

Wang, Xingsheng ; Brown, Andrew R. ; Cheng, Binjie ; Asenov, Asen

Author_Institution

Device Modelling Group, Univ. of Glasgow, Glasgow, UK

fYear

2011

fDate

5-7 Dec. 2011

Abstract

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.

Keywords

MOSFET; semiconductor device reliability; silicon-on-insulator; RDD; SOI substrate; comprehensive full-scale 3D simulation study; electrostatic integrity; gate length; interface trapped charge; line edge roughness; low channel doping; metal gate granularity; nanoscale FinFET; random discrete dopant; size 10 nm; size 14 nm; size 20 nm; statistical reliability; statistical variability; Correlation; Doping; FinFETs; Fluctuations; Logic gates; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131494

Filename

6131494