Title :
Unexpected failure during HBM ESD stress in nanometer-scale nLDMOS-SCR devices
Author :
Chen, S.-H. ; Thijs, S. ; Griffoni, A. ; Linten, D. ; De Keersgieter, A. ; Groeseneken, G.
Abstract :
Unexpected gate oxide failure has been observed during HBM ESD stress on high-voltage tolerant nLDMOS-SCR devices in standard low-voltage CMOS technology. TCAD simulations show that this early gate-oxide failure is due to high current injection originating from the additional discharge current of the inherent HBM board capacitance.
Keywords :
CMOS integrated circuits; MOS-controlled thyristors; electrostatic discharge; failure analysis; semiconductor device models; semiconductor device reliability; stress analysis; HBM ESD stress; HBM board capacitance; TCAD simulations; current injection; discharge current; high-voltage tolerant nLDMOS-SCR devices; human body model; nanometer-scale nLDMOS-SCR devices; standard low-voltage CMOS technology; unexpected gate oxide failure; Anodes; Current density; Electric potential; Electrostatic discharges; Logic gates; Silicon; Stress;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131501
