An approach for optimizing WIP/cycle time/output in a semiconductor fabricator

The relationships between work in progress (WIP), cycle time, and daily going rates (DGR) are relatively well understood. However, selecting parameters for optimum operation in a fabricator is more of an art form than an analytical process. This paper describes a process used in our 0.7 μm wafer fabricator at IBM Microelectronics in Essex Junction, Vermont, to optimize these parameters. This process uses real manufacturing-line data to quantify tool and organizational capabilities, which are then consolidated at the line level. Line and department targets are set to optimize unit costs, cycle time, and to drive day-to-day as well as long-term learning plans. In addition, this paper attempts to bridge empirical data to the queuing theory models