DocumentCode
3036837
Title
A non destructive scan diagnosis based fault isolation technique verification method using infrared laser stimulation on wafer level
Author
You, G.F. ; Goh, S.H. ; Yeoh, B.L. ; Hu, Haibo ; Chung, Nl ; Fei, Tai ; Yap, C.P. ; Lim, T.Y. ; Lam, James
Author_Institution
Technol. Dev., New Technol. Prototyping, GlobalFoundries, Singapore, Singapore
fYear
2013
fDate
15-19 July 2013
Firstpage
35
Lastpage
37
Abstract
Scan diagnosis based fault isolation technique using Electronic Design Automation (EDA) software tool is highly effective and commonly adopted for product chain and logic yield learning. For every new device introduction, prior to implementation of scan diagnosis for yield ramp, it is necessary to validate the success and accuracy of the test patterns generated for diagnosis. The accuracy of the fail suspects isolated is typically verified on physical failure analysis (PFA). In this paper, a non destructive verification methodology without the need for design information, die packaging and physical failure analysis is proposed. The contribution is a faster turnaround time for success qualification. The experimental data in this work demonstrates the feasibility and presents an added application for wafer level laser diagnostics.
Keywords
electronic design automation; failure analysis; laser materials processing; software tools; EDA software tool; design information; die packaging; electronic design automation; fault isolation technique verification method; infrared laser stimulation; logic yield learning; nondestructive scan diagnosis; nondestructive verification methodology; physical failure analysis; product chain; success qualification; turnaround time; wafer level laser diagnostics; yield ramp; Accuracy; Circuit faults; Failure analysis; Laser beams; Laser theory; Measurement by laser beam; ATE (Automatic Test Equipment); Laser Assisted Device Alteration (LADA); Scan Chain diagnosis; Wafer level laser diagnostic;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the
Conference_Location
Suzhou
ISSN
1946-1542
Print_ISBN
978-1-4799-1241-4
Type
conf
DOI
10.1109/IPFA.2013.6599123
Filename
6599123
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