Title :
A high latchup - Immune ESD protection SCR-incorporated BJT in deep submicron technology
Author :
Chih-Yao Huang ; Fu-Chien Chiu ; Ji-Fan Chi ; Yi-Jou Huang ; Quo-Ker Chen ; Jen-Chou Tseng
Author_Institution :
Dept. of Electron. Eng., Chien Hsin Univ. of Sci. & Technol., Zhongli, Taiwan
Abstract :
An SCR-incorporated BJT for latchup and ESD optimization is developed in a 0.18μm-3.3V process. This device simply consists of a floating P+ region in a parasitic NPN BJT. Its optimized second breakdown current exceeds 80% that of an SCR and latchup triggering current is 2~4 times greater.
Keywords :
bipolar transistors; electrostatic discharge; thyristors; ESD optimization; deep submicron technology; floating P region; latchup-immune ESD protection SCR-incorporated BJT; optimized second breakdown current; parasitic NPN BJT; size 0.18 mum; triggering current; voltage 3.3 V; Failure analysis; Integrated circuits;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the
Conference_Location :
Suzhou
Print_ISBN :
978-1-4799-1241-4
DOI :
10.1109/IPFA.2013.6599129
