Coding-based transceiver for phased array with significant hardware reduction

We proposed a novel reduced hardware receiver architecture with on-site coding. The proposed system offers a substantial reduction in the number of ADCs, and hence, fewer FPGA I/O pins. This results in a significant SWAP-C reduction, making digital beamforming with multiple concurrent beams more practical for large arrays. The proposed system was successfully simulated for two signal paths with Walsh codes and preliminary simulations demonstrated the recovery of the signal with a minor degradation of 0.8 dB in E_b/N_o. This was compensated for by combining the signals in digital baseband resulting in a 2.2 dB combining gain.