Advanced interconnect technology

Summary form only given. As minimum feature size in multi-billion transistor chips scales to the 100 nm range and below, the relative importance of transistors and interconnects in determining the maximum clock frequency, power dissipation, size and cost of a chip is changing. Interconnects now tend to surpass transistors in terms of impact on these key chip metrics. This “tyranny” of interconnects can be mitigated by the following approaches: (1) invention of new communication centric architectures; (2) development of new compact models that describe accurately the massive inductive and capacitive coupling that occurs in multilevel interconnect networks; (3) the use of on-chip and chip-to-chip optical interconnects; (4) ultra-high density electrical input/output interconnects and chip packages batch fabricated at the wafer level; (5) three-dimensional structures using multiple levels of transistors and interconnects; and (6) predictive process, property and performance models for interconnects as well as novel metrology tools to support them. These approaches are under investigation in a long-range research program with a ten-year horizon involving six universities, which operate coherently as the Interconnect Focus Center