Title :
CLP-based multifrequency test generation for analog circuits
Author :
Abderrahman, A. ; Cerny, E. ; Kaminska, B.
Author_Institution :
Dept. de Genie Electr. et d´´Inf., Ecole Polytech. de Montreal, Que., Canada
fDate :
27 Apr-1 May 1997
Abstract :
In our previous work we elaborated a multifrequency test generation method (TPG) for detecting parametric and catastrophic faults in linear analog circuits. The method was formulated as an optimization problem which was solved by Sequential Quadratic Programming (SQP), a non-linear programming method available in MATLAB. Such standard optimization methods are based on and process local information and consequently cannot guarantee a global optimum. In this paper we propose a method based on Constraint Logic Programming (CLP) that solves the optimization problem in TPG as a series of Constraint Satisfaction Problems (CSPs). Our TPG method is fully automatic and provides right and guaranteed bounds on the global optima of a nonlinear function. The TPG method was implemented in CLP(BNR) Prolog. First, we illustrate the effectiveness of our approach on a number of nonlinear functions known to be difficult, and then we apply it to a realistic electronic circuit in the context of TPG. The two methods produce the same results except for one case where SQP falls into a local minimum. This could lead to a wrong test selection. Moreover, while the TPG took over a week of work using SQP, it was solved in a matter of minutes using CLP
Keywords :
PROLOG; VLSI; analogue integrated circuits; automatic testing; circuit optimisation; constraint handling; integrated circuit testing; CLP-based multifrequency test generation; Prolog; constraint logic programming; constraint satisfaction problems; global optima; linear analog circuits; optimization problem; test selection; Analog circuits; Circuit faults; Circuit testing; Constraint optimization; Electrical fault detection; Fault detection; Logic programming; MATLAB; Optimization methods; Quadratic programming;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600241