Low-power, low-noise adder design with pass-transistor adiabatic logic

Author

Mahmoodi-Meimand, Hamid ; Afzali-Kusha, Ali

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

2000

fDate

2000

Firstpage

61

Lastpage

64

Abstract

In this paper, the efficiency of a fully adiabatic logic circuit is compared with its combinational and pipelined static CMOS counterparts. The performance of each circuit is studied in terms of the maximum operating frequency, the minimum operating voltage, the circuit energy consumption, and the switching noise generated by the circuit. An 8-bit carry look-ahead adder is designed using a 0.6 μm CMOS technology for all three logic styles. Based on the post-layout simulation results, the adiabatic adder exhibits energy savings of 76% to 87% and 87% to 90% compared to its combinational and pipelined static CMOS counterparts, respectively. It also exhibits a considerable reduction in switching noise compared to its static CMOS counterparts

Keywords

CMOS logic circuits; circuit simulation; combinational circuits; integrated circuit design; integrated circuit noise; logic CAD; logic simulation; pipeline processing; 0.6 micron; 8 bit; CMOS technology; adiabatic adder; carry look-ahead adder; circuit energy consumption; circuit performance; combinational CMOS logic; energy savings; fully adiabatic logic circuit; logic style; low-noise adder design; low-power adder design; maximum operating frequency; minimum operating voltage; pass-transistor adiabatic logic; pipelined static CMOS logic; post-layout simulation; switching noise; Adders; CMOS logic circuits; CMOS technology; Circuit noise; Energy consumption; Frequency; Logic circuits; Noise generators; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916415

Filename

916415