Title :
Delay optimization and energy estimation in CMOS differential cascade voltage switch logic circuits
Author :
Shams, Maitham ; Elmasry, Mohamed
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
Abstract :
This paper presents closed-form expressions for delay optimization in CMOS DCVSL circuits. It also introduces a method of estimating the delay and energy in such circuits. The results reported in this paper based on our technique are in good agreement with HSPICE simulation results
Keywords :
CMOS logic circuits; SPICE; cascade networks; circuit optimisation; circuit simulation; delay estimation; integrated circuit modelling; logic simulation; parameter estimation; CMOS DCVSL circuits; CMOS differential cascade voltage switch logic circuits; HSPICE simulation; closed-form expressions; delay estimation; delay optimization; energy estimation; Adders; CMOS logic circuits; Capacitance; Circuit simulation; Delay estimation; Logic circuits; MOSFETs; Switches; Switching circuits; Voltage;
Conference_Titel :
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location :
Tehran
Print_ISBN :
964-360-057-2
DOI :
10.1109/ICM.2000.916416
