Title :
Comparison of 32-bit multipliers for various performance measures
Author :
Shah, Shalin ; Al-Khalili, A.J. ; Khalili, D. Al
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tree multiplier, combined modified Booth-Wallace tree multiplier and twin pipe serial parallel multiplier. Comparison is based on synthesis results obtained by synthesizing all multiplier architectures towards FPGA
Keywords :
field programmable gate arrays; integrated circuit design; logic design; multiplying circuits; parallel architectures; 32 bit; FPGA; array multiplier; combined modified Booth-Wallace tree multiplier; integer multipliers; modified Booth (radix-4) multiplier; multiplier architecture synthesis; multipliers; optimized Wallace tree multiplier; performance measures; twin pipe serial parallel multiplier; Adders; Digital signal processing; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Parallel processing; Routing; Signal processing algorithms; Silicon; Very large scale integration;
Conference_Titel :
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location :
Tehran
Print_ISBN :
964-360-057-2
DOI :
10.1109/ICM.2000.916418
