Author :
Cho, H.-J. ; Seo, K.-I. ; Jeong, W.C. ; Kim, Y.-H. ; Lim, Y.D. ; Jang, W.W. ; Hong, J.G. ; Suk, S.D. ; Li, M. ; Ryou, C. ; Rhee, H.S. ; Lee, J.G. ; Kang, H.S. ; Son, Y.S. ; Cheng, C.L. ; Hong, S.H. ; Yang, W.S. ; Nam, S.W. ; Ahn, J.H. ; Lee, D.H. ; Park,
Author_Institution :
Logic TD & Process Dev. 3PJT, Samsung Electron., Hwasung, South Korea
Abstract :
A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 μA/μm and 756 μA/μm respectively at 0.9 V and 1 nA/μm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; high-k dielectric thin films; low-power electronics; DIBL; SRAM device; bulk planar high-k-metal gate CMOS technology; contacted-poly pitch; high performance application; logic device technology; low power application; nFET drive currents; optimized shallow junction; pFEL drive currents; short channel effect; size 20 nm; strain engineering; subthreshold swing; High K dielectric materials; Junctions; Logic gates; Metals; Performance evaluation; Random access memory; Strain;
