Improving the energy/power constraint for technology optimization

Consideration of energy and power constraints is critical in establishing roadmap projections for future generations of CMOS technology. We introduce a new optimization constraint, energy × power density, which better reflects actual design goals and compromises, and use it to evaluate technology scaling trends. We highlight differences from conventional expectations about scaling, including the need for separate targets for high-performance parallel designs versus single- thread designs, and include an evaluation of the prospects for low- temperature operation.