CMOS device design and optimization from a perspective of circuit-level energy-delay optimization

Currently, technology innovations focus on enhancing carrier transport properties by introducing novel materials (e.g. III-V and Ge) and improving short channel electrostatic control by adopting novel structures (e.g. multi-gate). In this paper, we show that the performance benefits at the circuit-level depend strongly on the target applications and load scenarios. Enhanced electrostatic control improves circuit-level energy-delay trade-off for both high-performance (HP) and low-power (LP) applications, while better transport only benefits the HP application. To achieve the optimal energy-delay trade-off at the circuit-level, P/N width ratio, supply voltage (V_dd), and width-normalized off-state current (I_off) must be optimized for the target application and load scenario.