Failure analysis approach For TrenchMOS devices

TrenchMOS FET devices fabricated vertically instead of conventional horizontal POWERMOS devices. Conventional failure analysis techniques have shown difficulty in identifying the failing location if the defect happens at the bottom of trench. Different failure analysis techniques have been developed to analyze the low yield wafers. This paper demonstrates the use of various failure analysis techniques to isolate the defective location and assisting Fab process team to resolve the issue and improve yield.