Thin silicon wafer processing and strength characterization

Thin silicon die (100 um or less) are required for a number of applications, including stacked die packages and three-dimensional integrated circuits (3D-IC). The wafer thinning process is conceptually simple, but requires optimization of the backside finish and dicing to ensure high die strength. High die strength is required to minimize yield loss during assembly and to ensure high reliability during device operation. In this paper, we describe process optimization for thin wafers and thin die, and how these processes affect the fracture strength of silicon.